Zen 5

CPUID codeFamily 1AhCacheL1 cache80 KiB (per core):
L2 cache1 MiB (per core)L3 cacheArchitecture and classificationTechnology nodeTSMC N4P (Zen 5)
TSMC N3 (Zen 5c in Turin Dense)
TSMC N6 (IOD)Instruction setAMD64 (x86-64)ExtensionsPhysical specificationsCoresMemory (RAM)SocketsProducts, models, variantsProduct code namesBrand namesHistoryPredecessorZen 4

Zen 5 is the name for a CPU microarchitecture by AMD, shown on their roadmap in May 2022,^[3] launched for mobile in July 2024 and for desktop in August 2024.^[4] It is the successor to Zen 4 and is currently fabricated on TSMC's N4P process.^[5] Zen 5 is also planned to be fabricated on the N3E process in the future.^[6]

The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), Epyc 9005 server processors (codenamed "Turin"),^[7] and Ryzen AI 300 thin and light mobile processors (codenamed "Strix Point").^[8]

A roadmap shown during AMD's Financial Analyst Day on June 9, 2022 confirmed that Zen 5 and Zen 5c would be launching in 3nm and 4nm variants in 2024.^[9] The earliest details on the Zen 5 architecture promised a "re-pipelined front end and wide issue" with "integrated AI and Machine Learning optimizations".

During AMD's Q4 2023 earnings call on January 30, 2024, AMD CEO Lisa Su stated that Zen 5 products would be "coming in the second half of the year".^[10]

Zen 5 is a ground-up redesign of Zen 4 with a wider front-end, increased floating point throughput and more accurate branch prediction.^[11]

Zen 5 was designed with both 4nm and 3nm processes in mind. This acted as an insurance policy for AMD in the event that TSMC's mass production of its N3 nodes were to face delays, significant wafer defect issues or capacity issues. One industry analyst estimated early N3 wafer yields to be at 55% while others estimated yields to be similar to those of N5 at between 60-80%.^[12][13] Additionally, Apple, as TSMC's largest customer, is given priority access to the latest process nodes. In 2022, Apple was responsible for 23% of TSMC's $72 billion in total revenue.^[14] After N3 began ramping at the end of 2022, Apple bought up the entirety of TSMC's early N3B wafer production capacity to fabricate their A17 and M3 SoCs.^[15] Zen 5 Processors will continue to use the TSMC N6 node for the I/O die fabrication.^[16]

Zen 5's CCDs are fabricated on TSMC's N4P node.^[5] N4P offers a 11% more performance, 22% less power at the same performance and 6% density improvement over N5 which was used to produce Zen 4 CCDs. Zen 5c CCDs for Turin Dense server processors are fabricated on TSMC's N3 node.

The L1 cache per core is increased from 64 KiB to 80 KiB per core. The L1 instruction cache remains the same at 32 KiB but the L1 data cache is increased from 32 KiB to 48 KiB per core. Furthermore, the bandwidth of the L1 data cache for 512-bit floating point unit pipes has also been doubled. Zen 5 contains 6 Arithmetic Logic Units (ALUs), up from 4 ALUs in prior Zen architectures. A greater number of ALUs that handle common integer operations can increase per-cycle scalar integer throughput by 50%.^[17]

Zen 4 introduced AVX-512 instructions. AVX-512 capabilities have been expanded with Zen 5 with a doubling of the floating point pipe width to 512-bit. Additionally, there is greater bfloat16 throughput which is beneficial for AI workloads.

Other features and improvements, compared to Zen 4, include:

• A ~16% IPC uplift on average, claimed by AMD.^[18]
• Memory speeds up to DDR5-5600 and LPDDR5X-7500 are officially supported.^[19]
• Infinity Fabric clock (FCLK) has been increased to 2400 MHz.^[20]
• New 2-ahead branch predictor^[21]

Zen 4 vs Zen 5 capabilities^[22]

Attribute	Zen 4	Zen 5
L1/L2 BTB	1.5K/7K	16K/8K
Return Address Stack	32	52
ITLB L1/L2	64/512	64/2048
Fetched/Decoded Instruction Bytes/cycle	32	64
Op Cache associativity	12-way	16-way
Op Cache bandwidth	9 macro-ops	12 inst or fused inst
Dispatch bandwidth (macro-ops/cycle)	6	8
AGU Scheduler	3x24 ALU/AGU	56
ALU Scheduler	1x24 ALU	88
ALU/AGU	4/3	6/4
Int PRF (red/flag)	224/126	240/192
Vector Reg	192	384
FP Pre-Sched Queue	64	96
FP Scheduler	2x32	3x38
FP Pipes	3	4
Vector Width	256	256b/512b
ROB/Retire Queue	320	448
LS Mem Pipes support Load/Store	3/1	4/2
DTLB L1/L2	72/3072	96/4096
L1Data Cache	32 KiB/8-way	48 KiB/12-way
L2 per core	1 MiB/8w	1 MiB/16w
L2 bandwidth	32B/clk	64B/clk

AMD announced an initial lineup of four models of Ryzen 9000 processors on June 3, 2024, including one Ryzen 5, one Ryzen 7 and two Ryzen 9 models. Manufactured on a 4 nm process, the processors feature between 6 and 16 cores.^[18] Ryzen 9000 processors were released in August.

Common features of Ryzen 9000 desktop CPUs:

• Socket: AM5.
• All the CPUs support DDR5-5600 in dual-channel mode.
• All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
• Includes integrated RDNA2 GPU with 2 CUs and base, boost clock speeds of 0.4 GHz, 2.2 GHz.
• L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Fabrication process: TSMC N4 FinFET (N6 FinFET for the I/O die).

Branding and Model		Cores (threads)	Clock rate (GHz)		L3 cache (total)	TDP	Chiplets	Core config[i]	Release date	Launch price[a]
			Base	Boost
Ryzen 9	9950X[23][24]	16 (32)	4.3	5.7	64 MB	170 W	2 × CCD 1 × I/OD	2 × 8	August 15, 2024	US $649
	9900X[23][24]	12 (24)	4.4	5.6		120 W		2 × 6		US $499
Ryzen 7	9700X[23][24]	8 (16)	3.8	5.5	32 MB	65 W	1 × CCD 1 × I/OD	1 × 8	August 8, 2024	US $359
Ryzen 5	9600X[23][24]	6 (12)	3.9	5.4				1 × 6		US $279

The Ryzen AI 300 series of high-performance ultrathin notebook processors were announced on June 3, 2024. Codenamed Strix Point, these processors are named under a new model numbering system similar to Intel's Core and Core Ultra model numbering. Strix Point will feature a 3rd gen Ryzen AI engine based on XDNA 2, providing up to 50 TOPS of neural processing unit performance. The integrated graphics is upgraded to RDNA 3.5, and top end models will have 16 CUs of GPU and 12 cores of CPU, an increase from the maximum of 8 CPU cores on previous generation Ryzen ultrathin mobile processors.^[25] Notebooks featuring Ryzen AI 300 series processors were released on July 17.^[26]

Common features of Ryzen AI 300 notebook APUs:

• Socket: BGA, FP8 package type.
• All models support DDR5-5600 or LPDDR5X-7500 in dual-channel mode.
• All models support 16 PCIe 4.0 lanes.
• iGPU uses the RDNA 3.5 microarchitecture.
• NPU uses the XDNA 2 AI Engine (Ryzen AI).
• Both Zen5 and Zen5c cores support AVX-512 using a half-width 256-bit FPU.
• L1 cache: 80 KB (48 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Fabrication process: TSMC N4P FinFET.

Branding and Model		CPU						GPU		NPU (Ryzen AI)	TDP	Release date
		Cores (threads)			Clock (GHz)		L3 cache (total)	Model	Clock (GHz)
		Total	Zen 5	Zen 5c	Base	Boost[a]
Ryzen AI 9	HX 375	12 (24)	4 (8)	8 (16)	2.0	5.1	24 MB	890M 16 CUs	2.9	55 TOPS	15–54 W	July 17, 2024
	HX 370[28]									50 TOPS
	365[28]	10 (20)		6 (12)		5.0		880M 12 CUs
Ryzen AI 7	PRO 360[29]	8 (16)	3 (6)	5 (10)		5.1	8 MB	870M	TBA	TBA	TBA	TBA
	PRO 160[30]					4.2

Alongside Granite Ridge desktop and Strix Point mobile processors, the Epyc 9005 series of high-performance server processors, codenamed Turin, were also announced at Computex on June 3, 2024. It uses the same SP5 socket as the previous Epyc 9004 series processors, and will pack up to 128 cores and 256 threads on the top-end model. Turin will be built on a TSMC 4 nm process.^[31]

A variant of Epyc 9005 using Zen 5c cores was also shown off at Computex. It will feature a maximum of 192 cores and 384 threads, and be manufactured on a 3 nm process.^[31]

Zen 5c is a compact variant of the Zen 5 core, primarily targeted at hyperscale cloud compute server customers.^[32] It will succeed the Zen 4c core.